1. Field of the Invention
The present invention relates to a LCD device using a horizontal electric field, and more particularly to a thin film transistor substrate using a horizontal electric field type Liquid Crystal Display (LCD) device and a fabricating method thereof that are capable of simplifying a fabricating process.
2. Description of the Related Art
Generally, LCD device (LCD) devices control light transmittance of liquid crystal using an electric field to display a picture. The LCD devices are largely classified into a vertical electric field type LCD device and a horizontal electric field type LCD device depending on the direction that an electric field drives the liquid crystal material.
The vertical electric field type LCD device device drives the liquid crystal material in a twisted nematic (TN) mode with a vertical electric field formed between a pixel electrode and a common electrode arranged opposite to each other on the upper and lower substrates. The vertical electric field type LCD device has an advantage of a large aperture ratio while having a drawback of a narrow viewing angle about 90°.
The horizontal electric field type LCD device device drives liquid crystal material in an in plane switch (IPS) mode with a horizontal electric field formed between the pixel electrode and the common electrode arranged parallel to each other on the lower substrate. The horizontal electric field type LCD device has an advantage of an wide viewing angle about 160°.
Hereinafter, horizontal electric field type LCD device will be described in detail. The horizontal electric field applying type LCD device includes a thin film transistor substrate (i.e., a lower substrate) and a color filter substrate (i.e., an upper substrate) joined with each other, a spacer for uniformly maintaining a cell gap between two substrates, and a liquid crystal material interposed in the cell gap. The thin film transistor substrate includes a plurality of signal wirings for forming a horizontal electric field for each pixel, a plurality of thin film transistors, and an alignment film coated thereon to align the liquid crystal material. The color filter substrate includes a color filter for implementing a color, a black matrix for preventing a light leakage and an alignment film coated thereon for aligning the liquid crystal material.
In such a LCD device, the thin film transistor substrate has a complicated fabrication process that leads to a significant increase in manufacturing cost, because the fabrication process involves a semiconductor process which includes a plurality of mask processes. To solve this problem, the thin film transistor substrate manufacturing process has been developed to reduce the number of mask processes, for example one mask process can accommodate several processes such as thin film deposition, cleaning, photolithography, etching, photo-resist stripping and inspection processes, or other suitable process. Recently, a four mask process, one less mask process than the current mask process, is becoming a standard mask process of the thin film transistor.
FIG. 1 is a plan view showing a structure of a thin film transistor substrate of horizontal electric type LCD device adopting the related art four-mask process, and FIG. 2 is a cross-sectional view of the thin film transistor substrate taken along lines I-I′ and II-II′ of FIG. 1. Referring to FIG. 1 and FIG. 2, the thin film transistor substrate includes a gate line 2 and a data line 4 provided on a lower substrate 45 intersecting each other and insulated from each other by a gate insulating film 46 therebetween, a thin film transistor 6 provided at an intersection of the gate line 2 and the date line 4, a pixel electrode 14 and a common electrode 18 provided at a pixel area defined by the intersection structure for forming a horizontal field, and a common line 16 connected to the common electrode 18. Furthermore, the thin film transistor substrate includes a storage capacitor 20 provided at an area where the pixel electrode 14 overlaps the common line 16, a gate pad 24 connected to the gate line 2, and a data pad 30 connected to the data line 4 and a common pad 36 connected to the common line 16. The gate line 2 is supplied with a gate signal and the data line 4 is supplied with a data signal and are provided in an intersection structure to defined a pixel area. The common line 16 is provided in parallel with the gate line 2 having the pixel area therebetween. In addition, the common line 16 is supplied with a reference voltage for driving the liquid crystal material.
The thin film transistor 6 includes a gate electrode 8 connected to the gate line 2, a source electrode 10 connected to the data line 4, and a drain electrode 12 connected to the pixel electrode 14. Furthermore, the thin film transistor 6 includes an active layer 48 overlapping the gate electrode 8 and having a gate insulating film 46 therebetween to define a channel between the source electrode 10 and the drain electrode 12. The thin film transistor 6 allows the pixel signal from the data line 4 to be charged and maintained in the pixel electrode 14 in response to the gate signal from the gate line 2.
The active layer 48 also overlaps the data line 4, a lower data pad electrode 32 and an upper storage electrode 22. An ohmic layer 50 is provided on the active layer 48 to make an ohmic contact with the data line 4, the source electrode 10, the drain electrode 12, the lower data pad electrode 32. The pixel electrode 14 is connected to the drain electrode 12 of the thin film transistor 6 via a first contact hole 13 defined by passing through a protective film 52 provided at the pixel area 5. Further, the pixel electrode 14 includes a first horizontal part 14A connected to the drain electrode 12 and provided parallel with adjacent gate lines 2, a second horizontal part 14B overlapping the common line 16, and an extended portion 14C provided between the first and second horizontal parts 14A and 14B. The common electrode 18 is connected to the common line 16 and is provided at the pixel area 5. Specifically, the common electrode 18 is provided parallel with the extended portion 14C of the pixel electrode 14 at the pixel area 5.
Accordingly, a horizontal electric field is formed between the pixel electrode 14 to which a pixel signal is supplied via the thin film transistor 6 and the common electrode 18 to which a reference voltage is supplied via the common line 16. Particularly, the horizontal electric field is formed between the extended portion 14C of the pixel electrode 14 and the extended portion of common electrode 18. A liquid crystal material arranged in the horizontal direction by the horizontal electric field between the thin film transistor substrate and the color filter substrate by such a horizontal electric field are rotated due to dielectric anisotropy. Transmittance of light to the pixel area 5 is varied depending on a rotation extent of the liquid crystal material, thereby implementing a gray level scale.
The storage capacitor 20 includes the common line 16, an upper storage electrode 22 overlapping the common line 16. The gate insulating film 46, the active layer 48 and the ohmic contact layer 50 are disposed between the common line 16 and the upper storage electrode 22, thereby insulating each other. A pixel electrode 14 connected to the upper storage electrode 22 via a second contact hole 21 provided at the protective film 52. The storage capacitor 20 allows a pixel signal charged in the pixel electrode 14 to be maintained until the next pixel signal is charged.
The gate line 2 is connected to a gate driver (not shown) via the gate pad 24. The gate pad 24 comprises a lower gate pad electrode 26 extended from the gate line 2, and an upper gate pad electrode 28 connected to the lower gate pad electrode 26 via a third contact hole 27 defined by passing through the gate insulating film 46 and the protective film 52. The data line 4 is connected to the data driver (not shown) via the data pad 30. The data pad 30 includes a lower data pad electrode 32 extended from the data line 4, and an upper data pad electrode 34 connected to the lower data pad electrode 32 via a fourth contact hole 33 defined by passing through the protective film 52. The common line 16 receives a reference voltage from an external reference voltage source (not shown) through the common pad 36. The common pad 36 comprises a lower common pad electrode 38 extended from the common line 16, and an upper common pad electrode 40 connected to the lower common pad electrode 38 via a fifth contact hole 39 defined by passing through the gate insulating film 46 and the protective film 52.
A method of fabricating the thin film transistor substrate having the above-mentioned structure using the four-round mask process will be described in detail with reference to FIGS. 3A to 3D.
Referring to FIG. 3A, a gate metal pattern group including the gate line 2, the gate electrode 8, the lower gate pad electrode 26, the common line 16, the common electrode 18, and the lower common pad electrode 38 are provided on the lower substrate 45 by the first mask process. More specifically, a gate metal layer is formed on the upper substrate 45 by a deposition technique such as sputtering. Then, the gate metal layer is patterned by the photolithography and etching process using a first mask to form the gate metal pattern group. The gate metal layer is formed from a metal in an aluminum-group metal, such as chrome (Cr) or molybdenum (Mo).
Referring to FIG. 3B, the gate insulating film 46 is coated onto the lower substrate 45 provided with the gate metal pattern group. Then, a semiconductor pattern including the active layer 48 and the ohmic contact layer 50 are disposed followed by a source/drain metal pattern group including the data line 4, the source electrode 10, the drain electrode 12, the lower data pad electrode 32, and the upper storage electrode 22, by the second mask process.
More specifically, the gate insulating film 46, an amorphous silicon layer (i.e., active layer 48), an n+ amorphous silicon layer (i.e., ohmic contact layer 50) and a source/drain metal layer are sequentially disposed on the lower substrate 45 which is provided with the gate metal pattern group by deposition techniques such as plasma enhanced chemical vapor deposition (PECVD) and sputtering, or other suitable technique. The gate insulating film 46 is formed of an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx). The source/drain metal is formed of molybdenum (Mo), titanium (Ti), tantalum (Ta) or a molybdenum alloy, or other suitable material.
Then, a photo-resist pattern is formed on the source/drain metal layer by photolithography using a second mask. In this case, a diffractive exposure mask having a diffractive exposing part at a channel portion of the thin film transistor is used as a second mask, thereby allowing a photo-resist pattern of the channel portion to have a lower height than other source/drain pattern portion. Subsequently, the source/drain metal layer is patterned by a wet etching process using the photo-resist pattern to provide the source/drain metal pattern group.
Next, the n+ amorphous silicon layer (i.e., ohmic contact layer 50) and the amorphous silicon layer (i.e., active layer 48) are patterned simultaneously by a dry etching process using the same photo-resist pattern to provide the ohmic contact layer 50 and the active layer 48. The photo-resist pattern having a relatively low height is removed from the channel portion by the ashing process and thereafter the source/drain metal pattern and the ohmic contact layer 50 of the channel portion are etched by the dry etching process. Thus, the active layer 48 of the channel portion is exposed to disconnect the source electrode 10 from the drain electrode 12. Then, the photo-resist pattern left on the source/drain metal pattern group is removed by a stripping process.
Referring to FIG. 3C, the protective film 52 including first to fifth contact holes 13, 21, 27, 33 and 39 are formed on the gate insulating film 46 provided with the source/drain metal pattern group by the third mask process.
More specifically, the protective film 52 provided on the gate insulating film 46 is patterned by the photolithography and the etching process using the third mask to define the first to fifth contact holes 13, 21, 27, 33 and 39. The first contact hole 13 passes through the protective film 52 to expose the drain electrode 12, whereas the second contact hole 21 passes through the protective film 52 to expose the upper storage electrode 22. The third contact hole 27 passes through the protective film 52 and the gate insulating film 46 to expose the lower gate pad electrode 26. The fourth contact hole 32 passes through the protective film 52 to expose the lower data pad electrode 32. The fifth contact hole 30 passes through the protective film 52 and the gate insulating film 48 to expose the lower common pad electrode 38. If the source/drain metal is formed of a metal having a large dry-etching ratio such as molybdenum (Mo), then each of the first, second and fourth contact holes 13, 21 and 33 passes through the drain electrode 12, the upper storage electrode 22 and the lower data pad electrode 32 to expose the side portion of the source/drain metal pattern group. The protective film 50 is formed of an inorganic material identical to that of the gate insulating film 46, or an organic material having a low dielectric constant such as an acrylic organic compound, BCB (benzocyclobutene) or PFCB (perfluorocyclobutane), or other suitable material.
Referring to FIG. 3D, the transparent conductive film pattern group including the pixel electrode 14, the upper gate pad electrode 28, the upper data pad electrode 34 and the upper common pad electrode 40 are provided on the protective film 52 by the fourth mask process. More specifically, a transparent conductive film is coated onto the protective film 52 by a deposition technique such as sputtering, or other suitable technique. Then, the transparent conductive film is patterned by photolithography and the etching process using a fourth mask to provide the transparent conductive pattern group. The pixel electrode 14 is electrically connected to the drain electrode 12 via the first contact hole 13 and also is electrically connected to the upper storage electrode 22 via the second contact hole 21. The upper gate pad electrode 28 is electrically connected to the lower gate pad electrode 26 via the third contact hole 37. The upper data pad electrode 34 is electrically connected to the lower data pad electrode 32 via the fourth contact hole 33. The upper common pad electrode 40 is electrically connected to the lower common pad electrode 38 via the fifth contact hole 39. The transparent conductive film is formed of indium-tin-oxide (ITO), tin-oxide (TO) or indium-zinc-oxide (IZO), or other suitable material.
The related art thin film transistor substrate of horizontal electric field type LCD device and the fabricating method thereof as mentioned above adopts the four-round mask process, thereby reducing the number of fabricating processes and hence reducing a manufacturing cost compared with those using the five-round mask process. However, since the four-round mask process still has a complicated fabricating process to limit a further cost reduction, there has been required a scheme capable of simplifying the fabricating process even further to save the manufacturing cost.